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freescale data sheet: technical data contents ? freescale inc., 2008,2012. all rights reserved. document number: mpc5566 rev. 3, september 2012 this document provides electrical specifications, pin assignments, and package diagrams for the mpc5566 microcontroller device. for functional characteristics, refer to the mpc5566 microcontroller reference manual . 1 overview the mpc5566 microcontroller (mcu) is a member of the mpc5500 family of micr ocontrollers built on the power architecture ? embedded technology. this family of parts has many new features coupled with high performance cmos technology to provide substantial reduction of cost per feature and significant performance improvement over the mpc500 family. the host processor core of th is device complies with the power architecture embedded category that is 100% user-mode compatible (including floating point library) with the original powerpc instruction set.the embedded architecture enhancements improve the performance in embedded applicati ons. the core also has additional instructions, including digi tal signal processing (dsp) instructions, beyond the original powerpc instruction set. 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 emi (electromagnetic inte rference) characteristics 8 3.5 esd (electromagnetic stat ic discharge) characteris- tics9 3.6 voltage regulator controller (vrc) and power-on reset (por) electrical specifications9 3.7 power-up/down sequencing . . . . . . . . . . . . . . . . 10 3.8 dc electrical specifications. . . . . . . . . . . . . . . . . . 14 3.9 oscillator and fmpll electr ical characteristics . . 20 3.10 eqadc electrical characterist ics . . . . . . . . . . . . . 22 3.11 h7fa flash memory electrical characteristics . . . 23 3.12 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 fast ethernet ac timing specifications . . . . . . . . 46 4 mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.1 mpc5566 416 pbga pinout . . . . . . . . . . . . . . . . . 50 4.2 mpc5566 416-pin package dimensions . . . . . . . 53 5 revision history for the mpc5566 data sheet . . . . . . . 55 5.1 information changed between revisions 2.0 and 3.0 55 5.2 information changed between revisions 1.0 and 2.0 55 5.3 information changed between revisions 0.0 and 1.0 57 mpc5566 microcontroller data sheet
mpc5566 microcontroller data sheet, rev. 3 overview freescale semiconductor 2 the mpc5500 family of parts contains many new features coupled with high performance cmos technology to provide significant perf ormance improvement over the mpc565x. the host processor core of the mp c5566 also includes an instruction set enhancement allowing variable length encoding (vle). this allows optional encoding of mixed 16- and 32-bit instructions. with this enhancement, it is possible to significa ntly reduce the code size footprint. the mpc5566 has two levels of memory hierarchy. the fastest accesses are to the 32-kilobytes (kb) unified cache. the next level in the hierarchy cont ains the 128-kb on-chip in ternal sram and three- megabytes (mb) internal flash memory. the internal sram and flash memory hol d instructions and data. the external bus interface is designed to support mo st of the standard memories used with the mpc5 xx family. the complex input/output ti mer functions of the mpc5 566 are performed by two enhanced time processor unit (etpu) engines. each etpu e ngine controls 32 hardware channels , providing a total of 64 hardware channels. the etpu has b een enhanced over the tpu by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channe l, angle clock hardware, and additional control and arithmetic instructi ons. the etpu is programmed using a high-level programming language. the less complex timer functions of the mpc5566 ar e performed by the enhanc ed modular input/output system (emios). the emios? 24 hardware ch annels are capable of single-action, double-action, pulse-width modulation (pwm), a nd modulus-counter operations. moto r control capabilities include edge-aligned and center-aligned pwm. off-chip communication is performed by a suite of se rial protocols including controller area networks (flexcans), enhanced deserial/seria l peripheral interfaces (d spis), and enhanced serial communications interfaces (escis). the dspis suppor t pin reduction through hardware seri alization and deserialization of timer channels and general-purpos e input/output (gpios) signals. the mcu has an on-chip enhanced queued dual an alog-to-digital converter (eqadc).s 40-channels. the system integration unit (siu) performs several chip-wide configuration f unctions. pad configuration and general-purpose input and output (g pio) are controlled from the si u. external interrupts and reset control are also determined by th e siu. the internal multiplexer submodule provides multiplexing of eqadc trigger sources, daisy chaining the dspi s, and external interrupt signal multiplexing. the fast ethernet (fec) module is a risc-based controller that supports both 10 and 100 mbps ethernet/ieee? 802.3 networks and is compatible with three different standard mac (media access controller) phy (physical) in terfaces to connect to an external ethernet bus. the fec supports the 10 or 100 mbps mii (media independent inte rface), and the 10 mbps-only with a seven-wire interface, which uses a subset of the mii signals. the upper 16-bits of the 32-bit ex ternal bus interface (ebi) are used to connect to an external ethernet de vice. the fec contains built-in tran smit and receive message fifos and dma support.
ordering information mpc5566 microcontroller data sheet, rev. 3 freescale 3 2 ordering information figure 1. mpc5500 family part number example unless noted in this data sheet, all specifications apply from t l to t h . table 1. orderable part numbers freescale part number 1 1 all devices are ppc5566, rather than mpc55 66 or spc5566, until product qualifications are complete. not all configurations are available in the ppc parts. package description speed (mhz) operating temperature 2 2 the lowest ambient operating te mperature is referenced by t l ; the highest ambient operating te mperature is referenced by t h . nominal max. 3 (f max ) 3 speed is the nominal maximum frequency. max. speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; 135 mhz parts allow for 132 mhz system clock + 2% fm; and 147 mhz parts allow for 144 mhz system clock + 2% fm. min. (t l )max. (t h ) mpc5566mvr144 mpc5566 416 package lead-free (pbfree) 144 147 ?40 c 125 c MPC5566MVR132 132 135 mpc5566mvr112 112 114 mpc5566mvr80 80 82 mpc5566mzp144 mpc5566 416 package leaded (snpb) 144 147 ?40 c 125 c mpc5566mzp132 132 135 mpc5566mzp112 112 114 mpc5566mzp80 80 82 mpc m 80 r qualification status core code device number temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = ?40 c to 125 c package identifier zp = 416pbga snpb vr = 416pbga pb-free operating frequency 80 = 80 mhz 112 = 112 mhz 132 = 132 mhz 144 = 144 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 5566 zp note: not all options are available on all devices. refer to ta b l e 1 .
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for the mcu. 3.1 maximum ratings table 2. absolute maximum ratings 1 spec characteristic symbol min. max. unit 1 1.5 v core supply voltage 2 v dd ?0.3 1.7 v 2 flash program/erase voltage v pp ?0.3 6.5 v 4 flash read voltage v flash ?0.3 4.6 v 5 sram standby voltage v stby ?0.3 1.7 v 6 clock synthesizer voltage v ddsyn ?0.3 4.6 v 7 3.3 v i/o buffer voltage v dd33 ?0.3 4.6 v 8 voltage regulator control input voltage v rc33 ?0.3 4.6 v 9 analog supply voltage (reference to v ssa )v dda ?0.3 5.5 v 10 i/o supply voltage (fast i/o pads) 3 v dde ?0.3 4.6 v 11 i/o supply voltage (slow and medium i/o pads) 3 v ddeh ?0.3 6.5 v 12 dc input voltage 4 v ddeh powered i/o pads v dde powered i/o pads v in ?1.0 5 ?1.0 5 6.5 6 4.6 7 v 13 analog reference high voltage (reference to v rl )v rh ?0.3 5.5 v 14 v ss to v ssa differential voltage v ss ? v ssa ?0.1 0.1 v 15 v dd to v dda differential voltage v dd ? v dda ?v dda v dd v 16 v ref differential voltage v rh ? v rl ?0.3 5.5 v 17 v rh to v dda differential voltage v rh ? v dda ?5.5 5.5 v 18 v rl to v ssa differential voltage v rl ? v ssa ?0.3 0.3 v 19 v ddeh to v dda differential voltage v ddeh ? v dda ?v dda v ddeh v 20 v ddf to v dd differential voltage v ddf ? v dd ?0.3 0.3 v 21 v rc33 to v ddsyn differential voltage spec has been moved to ta b l e 9 dc electrical specifications, spec 43a. 22 v sssyn to v ss differential voltage v sssyn ? v ss ?0.1 0.1 v 23 v rcvss to v ss differential voltage v rcvss ? v ss ?0.1 0.1 v 24 maximum dc digital input current 8 (per pin, applies to all digital pins) 4 i maxd ?2 2 ma 25 maximum dc analog input current 9 (per pin, applies to all analog pins) i maxa ?3 3 ma 26 maximum operating temperature range 10 die junction temperature t j t l 150.0 o c 27 storage temperature range t stg ?55.0 150.0 o c
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 5 3.2 thermal characteristics the shaded rows in the following table indicat e information specific to a four-layer board. 28 maximum solder temperature 11 lead free (pb-free) leaded (snpb) t sdr ? ? 260.0 245.0 o c 29 moisture sensitivity level 12 msl ? 3 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stress beyond any of the listed maxima can affect device reliability or cause permanent damage to the device. 2 1.5 v 10% for proper operation. this parameter is specified at a maximum junc tion temperature of 150 o c. 3 all functional non-supply i/o pins are clamped to v ss and v dde , or v ddeh . 4 ac signal overshoot and undershoot of up to 2.0 v of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not li mited for this duration). 5 internal structures hold the voltage greater than ?1.0 v if the injection current li mit of 2 ma is met. keep the negative dc voltage greater than ?0.6 v on etpub[15] and sinb during the internal power-on reset (por) state. 6 internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specificatio n is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 7 internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (2 ma for all pins) and v dde is within the operating voltage specifications. 8 total injection current for all pins (including both digital and analog) must not exceed 25 ma. 9 total injection current for all analog input pins must not exceed 15 ma. 10 lifetime operation at these specif ication limits is not guaranteed. 11 moisture sensitivity profile per ipc/jedec j-std-020d. 12 moisture sensitivity per jedec test method a112. table 3. mpc5566 thermal characteristics spec mpc5566 thermal characteristic symbol 416 pbga unit 1 junction to ambient, natural convection (one-layer board) 1, 2 1 junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipati on of other board components, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. r ? ja 24 c/w 2 junction to ambient, natural co nvection (four-layer board 2s2p) 1, 3 3 per jedec jesd51-6 with the board horizontal. r ? ja 16 c/w 3 junction to ambient (@200 ft./min., one-layer board) r ? jma 18 c/w 4 junction to ambient (@200 ft./ min., four-layer board 2s2p) r ? jma 13 c/w 5 junction to board (four-layer board 2s2p) 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. r ? jb 8 c/w 6 junction to case 5 5 indicates the average thermal resistance between the die and t he case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate tem perature used for the case temperature. r ? jc 6c/w 7 junction to package top, natural convection 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt 2c/w table 2. absolute maximum ratings 1 (continued) spec characteristic symbol min. max. unit
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 6 3.2.1 general notes for specification s at maximum junction temperature an estimation of the device junction temperature, t j , can be obtained from the equation: t j = t a + (r ? ja ? p d ) where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference betw een the values determined for the single-layer (1s) board compared to a four-layer boa rd that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal re sistance is not a constant . the thermal resistance depends on the: ? construction of the applicati on board (number of planes) ? effective size of the board which cools the component ? quality of the thermal and elec trical connections to the planes ? power dissipated by adjacent components connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias le ave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single-layer board is within the normal range for the tightly packed printed circuit board. the valu e obtained on a board with the intern al planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depe nds on the power dissipation of the surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device.
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 7 at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r ? jb ? p d ) where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r ? jb = junction-to-board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air doe s not factor into the calcu lation, an acceptable value for the junction temperature is predictable. ensure th e application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient th ermal resistance: r ? ja = r ? jc + r ? ca where: r ? ja = junction-to-ambient thermal resistance ( o c/w) r ? jc = junction-to-case thermal resistance ( o c/w) r ? ca = case-to-ambient thermal resistance ( o c/w) r ? jc is device related and is not affected by other fact ors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounti ng arrangement on the printed circui t board, or change the thermal dissipation on the printed circuit board surrounding th e device. this descripti on is most useful for packages with heat sinks where 90% of the heat flow is through th e case to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case ther mal resistance describes when using a heat sink or where a s ubstantial amount of heat is dissipat ed from the top of the package. the junction-to-board thermal resistan ce describes the thermal performanc e when most of the heat is conducted to the printed circuit board. this model can be used to generate si mple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the devi ce in the application on a prototype board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top center of the p ackage case using the following equation: t j = t t + ( ? jt ? p d ) where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w)
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 8 the thermal characterization parameter is measured in compliance with the je sd51-2 specification using a 40-gauge type t thermoc ouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple junction rests on the package. place a smal l amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocouple wire flat against the package case to avoid m easurement errors caused by the co oling effects of the thermocouple wire. references: semiconductor equipment and materials inte rnational 3081 zanker rd. san jose, ca., 95134 (408) 943-6900 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 1. c.e. triplett and b. joiner, ?an experimental characteri zation of a 272 pbga within an automotive engine controller module,? proceedi ngs of semitherm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?therm al modeling of a pbga for air-cooled applica- tions,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measu rement and simulation of junction to board thermal resistance and its application in thermal modeling,? pro ceedings of semitherm, san diego, 1999, pp. 212?220. 3.3 package the mpc5566 is available in packaged form. read the package options in section 2, ?ordering information.? refer to section 4, ?mechanicals,? for pinouts and package drawings. 3.4 emi (electromagnetic in terference) characteristics table 4. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 199 5-03. qualification testing was performed on the mpc5554 and applied to the mpc5500 family as generic emi performance data. spec characteristic minimum typical maximum unit 1 scan range 0.15 ? 1000 mhz 2 operating frequency ? ? f max mhz 3v dd operating voltages ? 1.5 ? v 4v ddsyn , v rc33 , v dd33 , v flash , v dde operating voltages ? 3.3 ? v 5v pp , v ddeh , v dda operating voltages ? 5.0 ? v 6 maximum amplitude ? ? 14 2 32 3 2 measured with the single-chip emi program. 3 measured with the expanded emi program. dbuv 7 operating temperature ? ? 25 o c
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 9 3.5 esd (electromagnetic static discharge) characteristics 3.6 voltage regulator controller (v rc ) and power-on reset (por) electrical specifications the following table lists the v rc and por electrical specifications: table 5. esd ratings 1, 2 1 all esd testing conforms to cdf-aec -q100 stress test qualification for automotive grade integrated circuits. 2 device failure is defined as: ?if after exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametric and function al testing at room temperature and hot temperature. characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 ? c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second table 6. v rc and por electrical specifications spec characteristic symbol min. max. units 11.5 v (v dd ) por 1 negated (ramp up) asserted (ramp down) v por15 1.1 1.1 1.35 1.35 v 23.3 v (v ddsyn ) por 1 asserted (ramp up) negated (ramp up) asserted (ramp down) negated (ramp down) v por33 0.0 2.0 2.0 0.0 0.30 2.85 2.85 0.30 v 3 reset pin supply (v ddeh6 ) por 1, 2 negated (ramp up) asserted (ramp down) v por5 2.0 2.0 2.85 2.85 v 4 v rc33 voltage before v rc allows the pass transistor to start turning on v trans_start 1.0 2.0 v 5 when v rc allows the pass transistor to completely turn on 3, 4 v trans_on 2.0 2.85 v 6 when the voltage is greater than the voltage at which the v rc keeps the 1.5 v supply in regulation 5, 6 v vrc33reg 3.0 ? v current can be sourced ?40 o c11.0?ma 7 by v rcctl at tj: 25 o ci vrcctl 7 9.0 ? ma 150 o c 7.5 ? ma 8 voltage differential during power up such that: v dd33 can lag v ddsyn or v ddeh6 before v ddsyn and v ddeh6 reach the v por33 and v por5 minimums respectively. v dd33_lag ?1.0v
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 10 3.7 power-up/down sequencing power sequencing between th e 1.5 v power supply and v ddsyn or the reset power supplies is required if using an external 1.5 v power supply with v rc33 tied to ground (gnd). to avoid power-sequencing, v rc33 must be powered up within the specified operati ng range, even if the on-chip voltage regulator controller is not used. refer to section 3.7.2, ?power-up sequence (vrc33 grounded) , ? and section 3.7.3, ?power-down sequence (vrc33 grounded) . ? power sequencing requires that v dd33 must reach a certain voltage where the values are read as ones before the por signal negates. refer to section 3.7.1, ?input value of pins during por dependent on vdd33 . ? although power sequencing is not required between v rc33 and v ddsyn during power up, v rc33 must not lead v ddsyn by more than 600 mv or lag by more than 100 mv for the v rc stage turn-on to operate within specification. higher spikes in the emitte r current of the pass transistor occur if v rc33 leads or lags v ddsyn by more than these amounts. the value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. furthermore, when all of the pors negate, the system clock starts to toggle, adding another large increase of the current consumed by v rc33 . if v rc33 lags v ddsyn by more than 100 mv, the increase in current consumed can drop v dd low enough to assert the 1.5 v por again. oscillations are possible when the 9 absolute value of slew rate on power supply pins ? ? 50 v/ms 10 required gain at tj: i dd ? i vrcctl (@ f sys = f max ) 6 , 7 , 8, 9 ? 40 o c beta 10 60 ? ? 25 o c 65 ?? 150 o c 85 500 ? 1 the internal por signals are v por15 , v por33 , and v por5 . on power up, assert reset before the internal por negates. reset must remain asserted until the power supplies ar e within the operating conditions as specified in ta b l e 9 dc electrical specifications. on po wer down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. 2 v il_s ( ta b l e 9 , spec15) is guaranteed to scale with v ddeh6 down to v por5 . 3 supply full operating current for the 1.5 v supp ly when the 3.3 v supply reaches this range. 4 it is possible to reach the current limit during ramp up?do not treat this event as short circuit current. 5 at peak current for device. 6 requires compliance with freescale?s recommended board requ irements and transistor recommendations. board signal traces/routing from the v rcctl package signal to the base of the external pass transistor and between the emitter of the pass transistor to the v dd package signals must have a maximum of 100 nh inductance and minimal resistance (less than 1 ? ). v rcctl must have a nominal 1 ? f phase compensation capacitor to ground. v dd must have a 20 ? f (nominal) bulk capacitor (greater than 4 ? f over all conditions, including lifetime). plac e high-frequency bypass capacitors consisting of eight 0.01 ? f, two 0.1 ? f, and one 1 ? f capacitors around the package on the v dd supply signals. 7 i vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 = 3.1 v, v vrcctl = 2.2 v. 8 refer to ta b l e 1 for the maximum operating frequency. 9 values are based on i dd from high-use applications as explained in the i dd electrical specification. 10 beta represents the worst-case external transistor. it is measured on a per-part basis and calculated as (i dd ? i vrcctl ). table 6. v rc and por electrical specifications (continued) spec characteristic symbol min. max. units
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 11 1.5 v por asserts and stops the syst em clock, causing the voltage on v dd to rise until the 1.5 v por negates again. all osci llations stop when v rc33 is powered sufficiently. when powering down, v rc33 and v ddsyn have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. wh en not powering up or down, no delta between v rc33 and v ddsyn is required for the v rc to operate within specification. there are no power up/down sequencing requirements to prevent issues su ch as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during power up and power down varies depending on which supplies are powered. table 7 gives the pin state for the sequence cases fo r all pins with pad type pad_fc (fast type). table 8 gives the pin state for the sequence cases for a ll pins with pad type pad_mh (medium type) and pad_sh (slow type). the values in table 7 and table 8 do not include the effect of the weak-pull devices on the output pins during power up. before exiting the internal por state, the voltage on the pins go to a high-im pedance state until por negates. when the internal por negates, the functi onal state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device reference manual. if v dd is too low to correctly propagate the logic signals , the weak-pull devices can pull the signals to v dde and v ddeh . to avoid this condition, minimize the ramp time of the v dd supply to a time period less than the time required to enable the external circ uitry connected to the device outputs. table 7. pin status for fast pads during the power sequence v dde v dd33 v dd por pin status for fast pad output driver pad_fc (fast) low ? ? asserted low v dde low low asserted high v dde low v dd asserted high v dde v dd33 low asserted high impedance (hi-z) v dde v dd33 v dd asserted hi-z v dde v dd33 v dd negated functional table 8. pin status for medium and slow pads during the power sequence v ddeh v dd por pin status for medium and slow pad output driver pad_mh (medium) pad_sh (slow) low ? asserted low v ddeh low asserted high impedance (hi-z) v ddeh v dd asserted hi-z v ddeh v dd negated functional
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 12 during initial power ramp-up, when v stby is 0.6v or above. a typical cu rrent of 1-3ma and maximum of 4ma may be seen until v dd is applied. this current will not reoccur until v stby is lowered below v stby min. specification. figure 2 shows an approximate interpolation of the i stby worst-case specification to estimate values at different voltages and temperatures . the vertical li nes shown at 25 ? c, 60 ? c, and 150 ? c in figure 2 are the actual i dd_stby specifications (27d) listed in table 9 . figure 2. fi stby worst-case specifications
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 13 3.7.1 input value of pins during por dependent on v dd33 when powering up the device, v dd33 must not lag the latest v ddsyn or reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in table 6 , spec 8. this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and therefore cannot read the defaul t state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification applies during power up only. v dd33 has no lead or lag requirements when powering down. 3.7.2 power-up sequence (v rc33 grounded) the 1.5 v v dd power supply must rise to 1.35 v before the 3.3 v v ddsyn power supply and the reset power supply rises above 2.0 v. this ensures that di gital logic in the pll fo r the 1.5 v power supply does not begin to operate below the spec ified operation range lower limit of 1.35 v. because the internal 1.5 v por is disabled, the internal 3.3 v por or the reset power por must hold th e device in reset. since they can negate as low as 2.0 v, v dd must be within specification be fore the 3.3 v por and the reset por negate. figure 3. power-up sequence (v rc33 grounded) 3.7.3 power-down sequence (v rc33 grounded) the only requirement for the power-down sequence with v rc33 grounded is if v dd decreases to less than its operating range, v ddsyn or the reset power must decrease to less than 2.0 v before the v dd power increases to its operating range. this ensures that the digital 1.5 v logic, which is reset only by an ored por and can cause the 1.5 v supply to decrease less than its specification valu e, resets correctly. see table 6 , footnote 1. v ddsyn and reset power v dd 2.0 v 1.35 v v dd must reach 1.35 v before v ddsyn and the reset pow er reach 2.0 v
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 14 3.8 dc electrical specifications table 9. dc electrical specifications (t a = t l to t h ) spec characteristic symbol min max. unit 1 core supply voltage (average dc rms voltage) v dd 1.35 1.65 v 2 input/output supply vo ltage (fast input/output) 1 v dde 1.62 3.6 v 3 input/output supply voltage (s low and medium input/output) v ddeh 3.0 5.25 v 4 3.3 v input/output buffer voltage v dd33 3.0 3.6 v 5 voltage regulator control input voltage v rc33 3.0 3.6 v 6 analog supply voltage 2 v dda 4.5 5.25 v 8 flash programming voltage 3 v pp 4.5 5.25 v 9 flash read voltage v flash 3.0 3.6 v 10 sram standby voltage 4 v stby 0.8 1.2 v 11 clock synthesizer operating voltage v ddsyn 3.0 3.6 v 12 fast i/o input high voltage v ih_f 0.65 ? v dde v dde + 0.3 v 13 fast i/o input low voltage v il_f v ss ? 0.3 0.35 ? v dde v 14 medium and slow i/o input high voltage v ih_s 0.65 ? v ddeh v ddeh + 0.3 v 15 medium and slow i/o input low voltage v il_s v ss ? 0.3 0.35 ? v ddeh v 16 fast input hysteresis v hys_f 0.1 ? v dde v 17 medium and slow i/o input hysteresis v hys_s 0.1 ? v ddeh v 18 analog input voltage v indc v ssa ? 0.3 v dda + 0.3 v 19 fast output high voltage (i oh_f = ?2.0 ma) v oh_f 0.8 ? v dde ?v 20 slow and medium output high voltage i oh_s = ?2.0 ma i oh_s = ?1.0 ma v oh_s 0.80 ? v ddeh 0.85 ? v ddeh ?v 21 fast output low voltage (i ol_f = 2.0 ma) v ol_f ?0.2 ? v dde v 22 slow and medium output low voltage i ol_s = 2.0 ma i ol_s = 1.0 ma v ol_s ? 0.20 ? v ddeh 0.15 ? v ddeh v 23 load capacitance (fast i/o) 5 dsc (siu_pcr[8:9]) = 0b00 = 0b01 = 0b10 = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf 24 input capacitance (digital pins) c in ?7pf 25 input capacitance (analog pins) c in_a ?10pf 26 input capacitance: (shared digital and analog pins an[12]_ma[0]_sds , an[13]_ma[1]_sdo, an[14]_ma[2]_sdi, and an[15]_fck) c in_m ?12pf
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 15 27e operating current 1.5 v supplies @ 147 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8, 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 650 530 820 650 750 585 ma ma ma ma ma ma 27a operating current 1.5 v supplies @ 135 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8 , 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 630 500 785 630 710 550 ma ma ma ma ma ma 27b operating current 1.5 v supplies @ 114 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8 , 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 600 450 680 500 650 490 ma ma ma ma ma ma 27c operating current 1.5 v supplies @ 82 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8 , 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 490 360 545 400 530 395 ma ma ma ma ma ma 27d ram standby current. 12 i dd_stby @ 25 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 60 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 150 o c (tj) v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby ? ? ? ? ? ? ? ? ? 20 30 50 70 100 200 1200 1500 2000 ? a ? a ? a ? a ? a ? a ? a ? a ? a table 9. dc electrical specifications (t a = t l to t h ) (continued) spec characteristic symbol min max. unit
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 16 28 operating current 3.3 v supplies @ f max mhz v dd33 13 i dd_33 ? 2 + (values derived from procedure of footnote 13 ) ma v flash i vflash ?10ma v ddsyn i ddsyn ?15ma 29 operating current 5.0 v supplies (12 mhz adclk): v dda (v dda0 + v dda1 ) analog reference supply current (v rh , v rl ) v pp i dd_a i ref i pp ? ? ? 20.0 1.0 25.0 ma ma ma 30 operating current v dde supplies: 14 v ddeh1 v dde2 v dde3 v ddeh4 v dde5 v ddeh6 v dde7 v ddeh8 v ddeh9 i dd1 i dd2 i dd3 i dd4 i dd5 i dd6 i dd7 i dd8 i dd9 ? ? ? ? ? ? ? ? ? refer to footnote 14 ma ma ma ma ma ma ma ma ma 31 fast i/o weak pullup current 15 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v i act_f 10 20 20 110 130 170 ? a ? a ? a fast i/o weak pulldown current 15 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v 10 20 20 100 130 170 ? a ? a ? a 32 slow and medium i/o weak pullup/down current 15 3.0?3.6 v 4.5?5.5 v i act_s 10 20 150 170 ? a ? a 33 i/o input leakage current 16 i inact_d ?2.5 2.5 ? a 34 dc injection current (per pin) i ic ?2.0 2.0 ma 35 analog input current, channel off 17 i inact_a ?150 150 na 35a analog input current, shared analog / digital pins (an[12], an[13], an[14], an[15]) i inact_ad ?2.5 2.5 ? a 36 v ss to v ssa differential voltage 18 v ss ? v ssa ?100 100 mv 37 analog reference low voltage v rl v ssa ? 0.1 v ssa + 0.1 v 38 v rl differential voltage v rl ? v ssa ?100 100 mv 39 analog reference high voltage v rh v dda ? 0.1 v dda + 0.1 v 40 v ref differential voltage v rh ? v rl 4.5 5.25 v table 9. dc electrical specifications (t a = t l to t h ) (continued) spec characteristic symbol min max. unit
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 17 41 v sssyn to v ss differential voltage v sssyn ? v ss ?50 50 mv 42 v rcvss to v ss differential voltage v rcvss ? v ss ?50 50 mv 43 v ddf to v dd differential voltage v ddf ? v dd ?100 100 mv 43a v rc33 to v ddsyn differential voltage v rc33 ? v ddsyn ?0.1 0.1 19 v 44 analog input differential signal range (with common mode 2.5 v) v idiff ?2.5 2.5 v 45 operating temperature r ange, ambient (packaged) t a = (t l to t h )t l t h ? c 46 slew rate on power-supply pins ? ? 50 v/ms 1 v dde2 and v dde3 are limited to 2.25?3.6 v on ly if siu_eccr[ebts] = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if siu_eccr[ebts] = 1. 2 | v dda0 ? v dda1 | must be < 0.1 v. 3 v pp can drop to 3.0 v during read operations. 4 if standby operation is not required, connect v stby to ground. 5 applies to clkout, external bus pins, and nexus pins. 6 maximum average rms dc current. 7 eight-way cache enabled (l1csr0[corg] = 0b0). 8 average current measured on automotive benchmark. 9 peak currents can be higher on specialized code. 10 high use current measured while running optimized spe asse mbly code with all code and data 100% locked in cache (0% miss rate) with all channels of the emios and etpu running autonomously, plus the edma transferring data continuously from sram to sram. higher currents are possible if an ?idle? loop that crosses cache lines is run from cache. write code to avoid th is condition. 11 four-way cache enabled (l1csr0[corg] = 0b1) or (l1csr0[co rg] = 0b0 with l1csr0[wam] = 0b1, l1csr0[wid] = 0b1111, l1csr0[wdd] = 0b1111, l1csr0[awid] = 0b1, and l1csr0[awdd] = 0b1). 12 the current specification relates to aver age standby operation after sram has been loaded with data. for power up current see section 3.7, ?power-up/down sequencing ?, figure 2 . 13 power requirements for the v dd33 supply depend on the frequency of operation, load of all i/o pins, and the voltages on the i/o segments. refer to ta b l e 11 for values to calculate the power dissipation for a specific operation. 14 power requirements for each i/o segment are dependent on the freque ncy of operation and load of the i/o pins on a particular i/ o segment, and the voltage of the i/o segment. refer to table 10 for values to calculate power dissipation for specific operation. the total power consumption of an i/o segment is the sum of the individual power consumptions for each pin on the segment. 15 absolute value of current, measured at v il and v ih . 16 weak pullup/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types: pad_fc, pad_sh, and pad_mh. 17 maximum leakage occurs at maximum operat ing temperature. leakage current decreases by approximately one-half for each 8 o c to 12 o c, in the ambient temperature range of 50 o c to 125 o c. applies to pad types: pad_a and pad_ae. 18 v ssa refers to both v ssa0 and v ssa1 . | v ssa0 ? v ssa1 | must be < 0.1 v. 19 up to 0.6 v during power up and power down. table 9. dc electrical specifications (t a = t l to t h ) (continued) spec characteristic symbol min max. unit
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 18 3.8.1 i/o pad current specifications the power consumption of an i/o se gment depends on the usage of the pi ns on a particular segment. the power consumption is the sum of al l output pin currents for a segmen t. the output pin current can be calculated from table 10 based on the voltage, frequency, and lo ad on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 10 . table 10. i/o pad average dc current (t a = t l to t h ) 1 1 these values are estimates from simulation and are not tested. currents apply to output pins only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltage (v) drive select / slew rate control setting current (ma) 1 slow i drv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5 medium i drv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9 fast i drv_fc 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 21 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 19 3.8.2 i/o pad v dd33 current specifications the power consumption of the v dd33 supply dependents on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/ o segments. the output pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. the input pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad_sh and pad_mh pins. use li near scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . table 11. v dd33 pad average dc current (t a = t l to t h ) 1 1 these values are estimated from simulation and not tested. currents appl y to output pins for the fast pads only and to input pins for the slow and medium pads only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive select current (ma) inputs 1slowi 33_sh 66 0.5 3.6 5.5 na 0.003 2 medium i 33_mh 66 0.5 3.6 5.5 na 0.003 outputs 3 fast i 33_fc 66 10 3.6 3.6 00 0.35 466203.63.6010.53 566303.63.6100.62 666503.63.6110.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.70 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 14 56 50 3.6 3.6 11 0.67 15 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 20 3.9 oscillator and fmpll el ectrical characteristics table 12. fmpll electrical specifications (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symbol minimum maximum unit 1 pll reference frequency range: 1 crystal reference external reference dual controller (1:1 mode) f ref_crystal f ref_ext f ref_1:1 8 8 24 20 20 f sys ? 2 mhz 2 system frequency 2 f sys f ico ( min ) ? 2 rfd f max 3 mhz 3 system clock period t cyc ?1 ? f sys ns 4 loss of reference frequency 4 f lor 100 1000 khz 5 self-clocked mode (scm) frequency 5 f scm 7.4 17.5 mhz 6 extal input high voltage crystal mode 6 all other modes [dual controller (1:1), bypass, external reference] v ihext v ihext v xtal + 0.4 v (v dde5 ? 2) + 0.4 v ? ? v v 7 extal input low voltage crystal mode 7 all other modes [dual controller (1:1), bypass, external reference] v ilext v ilext ? ? v xtal ? 0.4 v (v dde5 ?? 2) ? 0.4 v v v 8 xtal current 8 i xtal 26ma 9 total on-chip stray capacitance on xtal c s_xtal ?1.5pf 10 total on-chip stray capacitance on extal c s_extal ?1.5pf 11 crystal manufacturer?s recommended capacitive load c l refer to crystal specification refer to crystal specification pf 12 discrete load capacitance to connect to extal c l_extal ? (2 ? c l ) ? c s_extal ? c pcb_extal 9 pf 13 discrete load capacitance to connect to xtal c l_xtal ? (2 ? c l ) ? c s_xtal ? c pcb_xtal 9 pf 14 pll lock time 10 t lpll ? 750 ? s 15 dual controller (1:1) clock skew (between clkout and extal) 11, 12 t skew ?2 2 ns 16 duty cycle of reference t dc 40 60 % 17 frequency unlock range f ul ?4.0 4.0 % f sys 18 frequency lock range f lck ?2.0 2.0 % f sys
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 21 19 clkout period jitter, measured at f sys max: 13, 14 peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over a 2 ms interval) c jitter ? ? 5.0 0.01 % f clkout 20 frequency modulation range limit 15 (do not exceed f sys maximum) c mod 0.8 2.4 %f sys 21 ico frequency f ico = [f ref_crystal ? (mfd + 4)] ?? (prediv + 1) 16 f ico = [f ref_ext ? (mfd + 4)] ?? (prediv + 1) f ico 48 f max mhz 22 predivider output frequency (to pll) f prediv 420 17 mhz 1 nominal crystal and external reference values are worst-case no t more than 1%. the device oper ates correctly if the frequency remains within 5% of the specification lim it. this tolerance range allows for a slight frequency drift of the crystals over t ime. the designer must thoroughly understand the drift margin of the source clock. 2 all internal registers retain data at 0 hz. 3 up to the maximum frequency rating of the device (refer to ta b l e 1 ). 4 loss of reference frequency is defined as t he reference frequency detected internally, wh ich transitions the pll into self-cloc ked mode. 5 the pll operates at self-clocked mode (scm) freq uency when the reference frequency falls below f lor . scm frequency is measured on the clkout ball with the divider set to di vide-by-two of the system clock. note: in scm, the mfd and prediv have no effect and the rfd is bypassed. 6 use the extal input high voltage parameter when using the flexcan oscillator in crystal mode (no quartz crystals or resonators). (v extal ? v xtal ) must be ? 400 mv for the oscillator?s compar ator to produce the output clock. 7 use the extal input low voltage parameter when using the fl excan oscillator in crystal mode (no quartz crystals or resonators). (v xtal ?v extal ) must be ? 400 mv for the oscillator?s compar ator to produce the output clock. 8 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. 9 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. 10 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crystal oscillator reference, the lock time also includes the crystal startup time. 11 pll is operating in 1:1 pll mode. 12 v dde = 3.0?3.6 v. 13 jitter is the average deviation from the programmed frequ ency measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider is set to divide-by-two. 14 values are with frequency modulation disabled. if frequency modu lation is enabled, jitter is the sum of (jitter + cmod). 15 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 16 f sys = f ico ? (2 rfd ). 17 maximum value for dual cont roller (1:1) mode is (f max ?? 2) with the predivider set to 1 (fmpll_syncr[prediv] = 0b001). table 12. fmpll electrical specifications (continued) (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symbol minimum maximum unit
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 22 3.10 eqadc electrical characteristics table 13. eqadc conversion specifications ( t a = t l to t h ) spec characteristic symbol minimum maximum unit 1 adc clock (adclk) frequency 1 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800 ks/s and the minimum value is based on 20 mhz oscillator clock frequency divided by a maximum 16 factor. f adclk 112mhz 2 conversion cycles differential single ended cc 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) adclk cycles 3 stop mode recovery time 2 2 stop mode recovery time begins when the adc control regist er enable bits are set until the adc is ready to perform conversions. t sr 10 ? ? s 4 resolution 3 3 at v rh ? v rl = 5.12 v, one least significant bit (lsb) = 1.25, mv = one count. ?1.25 ? mv 5 inl: 6 mhz adc clock inl6 ?4 4 counts 3 6 inl: 12 mhz adc clock inl12 ?8 8 counts 7 dnl: 6 mhz adc clock dnl6 ?3 4 4 guaranteed 10-bit mono tonicity. 3 4 counts 8 dnl: 12 mhz adc clock dnl12 ?6 4 6 4 counts 9 offset error with calibration offwc ?4 5 5 the absolute value of the offset error without calibration ? 100 counts. 4 5 counts 10 full-scale gain error with calibration gainwc ?8 6 6 the absolute value of the full scale gain error without calibration ? 120 counts. 8 6 counts 11 disruptive input injection current 7, 8, 9, 10 7 below disruptive current conditions, the channel being stressed has conversion values of: 0x3ff for analog inputs greater than v rh , and 0x000 for values less than v rl . this assumes that v rh ? v dda and v rl ? v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions. 8 exceeding the limit can cause a conversion error on both stressed and unstressed channels. transit ions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the value specified. to determine the value of the required current-limit ing resistor, calcula te resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10 this condition applies to two adjacent pads on the internal pad. i inj ?1 1 ma 12 incremental error due to injection current. all channels are 10 k ? < rs <100 k ? channel under test has rs = 10 k ? , i inj = i injmax , i injmin e inj ?4 4 counts 13 total unadjusted error (tue) for single ended conversions with calibration 11, 12, 13, 14, 15 11 the tue specification is always less than the sum of the inl, dnl, offset, and gain errors due to canceling errors. 12 tue does not apply to differential conversions. 13 measured at 6 mhz adc clock. tue with a 12 mhz adc clock is: ?16 counts < tue < 16 counts. 14 tue includes all internal device e rrors such as internal referenc e variation (75% ref, 25% ref). 15 depending on the input impedance, the analog input leakage current ( table 9 . dc electrical specifications, spec 35a) can affect the actual tue meas ured on analog channels an[12], an[13], an[14], an[15]. tue ?4 4 counts
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 23 3.11 h7fa flash memory electrical characteristics table 14. flash program and erase specifications (t a = t l to t h ) spec flash program characteristic symbol min. typical 1 1 typical program and erase times are calculated at 25 o c operating temperature using nominal supply values. initial max. 2 2 initial factory condition: ?? 100 ? program/erase cycles, 25 o c, using a typical supply voltage measured at a minimum system frequency of 80 mhz. max. 3 3 the maximum erase time o ccurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 3 doubleword (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. t dwprogram ? 10 ? 500 ? s 4 page program time 4 t pprogram ? 22 44 5 5 page size is 256 bits (8 words). 500 ? s 7 16 kb block pre-program and erase time t 16kpperase ?2654005000ms 9 48 kb block pre-program and erase time t 48kpperase ?3454005000ms 10 64 kb block pre-program and erase time t 64kpperase ?4155005000ms 8 128 kb block pre-program and erase time t 128kpperase ? 500 1250 7500 ms 11 minimum operating frequency for program and erase operations 6 6 the read frequency of the flash can range up to the ma ximum operating frequency. there is no minimum read frequency condition. ?25???mhz table 15. flash eeprom module life (t a = t l to t h ) spec characteristic symbol min. typical 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical enduran ce, refer to engineering bulletin eb619 typical endurance for nonvolatile memory. unit 1a number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 1b number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) p/e 1000 100,000 cycles 2 data retention blocks with 0? 1,000 p/e cycles blocks with 1,00 1?100,000 p/e cycles retention 20 5 ? ? years
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 24 table 16 shows the flash_biu settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. 3.12 ac specifications 3.12.1 pad ac specifications table 16. flash_biu settings vs. frequency of operation 1 1 illegal combinations exist. use entrie s from the same row in this table. maximum frequency (mhz) apc rwsc wwsc dpfen 2 2 for maximum flash performance, set to 0b11. ipfen 2 pflim 3 3 for maximum flash performance, set to 0b110. bfen 4 4 for maximum flash performance, set to 0b1. up to and including 82 mhz 5 5 82 mhz parts allow for 80 mhz system clock + 2% frequency modulation (fm). 0b001 0b001 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 102 mhz 6 6 102 mhz parts allow for 100 mhz system clock + 2% fm. 0b001 0b010 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 135 mhz 7 7 135 mhz parts allow for 132 mhz system clock + 2% fm. 0b010 0b011 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 147 mhz 8 8 147 mhz parts allow for 144 mhz system clock + 2% fm. 0b011 0b100 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 26 15 50 82 60 200 01 75 40 50 137 80 200 00 377 200 50 476 260 200
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 25 2 medium high voltage (mh) 11 16 8 50 43 30 200 01 34 15 50 61 35 200 00 192 100 50 239 125 200 3fast 00 3.1 2.7 10 01 2.5 20 10 2.4 30 11 2.3 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9000 50 1 these are worst-case values that are estimated from simulati on (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 1.62?1.98 v; v ddeh = 4.5?5.25 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a =t l to t h . 2 this parameter is supplied for reference and is guaranteed by design (not tested). 3 the output delay is shown in figure 4 . to calculate the output delay wi th respect to the system clock, add a maximum of one system clock to the output delay. 4 the output delay and rise and fall are measur ed to 20% or 80% of the respective signal. 5 this parameter is guaranteed by charac terization rather than 100% tested. table 18. derated pad ac specifications (v ddeh = 3.3 v, v dde = 3.3 v) 1 spec pad src/dsc (binary) out delay 2, 3, 4 (ns) rise / fall 3 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium high voltage (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 (continued) spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf)
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 26 figure 4. pad output delay 3.13 ac timing 3.13.1 reset and configuration pin timing 3fast 00 3.2 2.4 10 01 2.2 20 10 2.1 30 11 2.1 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9500 50 1 these are worst-case values that are es timated from simulation (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 3.0?3.6 v; v ddeh = 3.0?3.6 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a = t l to t h . 2 this parameter is supplied for reference and guaranteed by design (not tested). 3 the output delay, and the rise and fall, are calcul ated to 20% or 80% of the respective signal. 4 the output delay is shown in figure 4 . to calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. 5 this parameter is guaranteed by characterization rather than 100% tested. table 19. reset and configuration pin timing 1 spec characteristic symbol min. max. unit 1 reset pulse width t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc table 18. derated pad ac specifications (v ddeh = 3.3 v, v dde = 3.3 v) 1 (continued) spec pad src/dsc (binary) out delay 2, 3, 4 (ns) rise / fall 3 , 5 (ns) load drive (pf) v dd ?? 2 v oh v ol rising-edge out delay falling-edge pad internal data pad output out delay input signal
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 27 figure 5. reset and configuration pin timing 3.13.2 ieee 1149.1 interface timing 3 pllcfg, bootcfg, wkpcfg, rstcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllcfg, bootcfg, wkpcfg, rstcfg hold time from rstout valid t rch 0?t cyc 1 reset timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . table 20. jtag pin ac electrical characteristics 1 spec characteristic symbol min. max. unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde ? 2) t jdc 40 60 ns 3 tck rise and fall times (40% to 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling-edge to output valid t bsdv ?50ns table 19. reset and configuration pin timing 1 (continued) spec characteristic symbol min. max. unit 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg rstcfg
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 28 figure 6. jtag test clock input timing 12 tck falling-edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling-edge to output high impedance (hi-z) t bsdhz ?50ns 14 boundary scan input valid to tck rising-edge t bsdst 50 ? ns 15 tck rising-edge to boundary scan input invalid t bsdht 50 ? ns 1 these specifications apply to jtag bound ary scan only. jtag timing specified at: v dde = 3.0?3.6 v and t a = t l to t h . refer to ta b l e 2 1 for nexus specifications. table 20. jtag pin ac electrical characteristics 1 (continued) spec characteristic symbol min. max. unit tck 1 2 2 3 3
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 29 figure 7. jtag test access port timing figure 8. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 30 figure 9. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 31 3.13.3 nexus timing figure 10. nexus output timing table 21. nexus debug port timing 1 1 jtag specifications apply when used for debug functionality. all nexus timing rela tive to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.35?1.65 v, v dde = 2.25?3.6 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10. spec characteristic symbol min. max. unit 1 mcko cycle time t mcyc 1 2 2 the nexus aux port runs up to 82 mhz. set npc_pcr[ mcko_div] to divide-by-two if the system frequency is greater than 82 mhz. 8t cyc 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until t he next mcko low cycle occurs. t mdov ?1.5 3.0 ns 4 mcko low to mseo data valid 3 t mseov ?1.5 3.0 ns 5 mcko low to evto data valid 3 t evtov ?1.5 3.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1?t mcyc 8 tck cycle time t tcyc 4 4 4 limit the maximum frequency to approximately 16 mhz (v dde = 2.25?3.0 v) or 20 mhz (v dde = 3.0?3.6 v) to meet the timing specification for t jov of [0.2 x t jcyc ] as outlined in the ieee-is to 5001-2003 specification. ?t cyc 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 5?ns 12 tck low to tdo data valid t jov v dde = 2.25?3.0 v 0 12 ns v dde = 3.0?3.6 v 0 10 ns 13 rdy valid to mcko 5 5 the rdy pin timing is asynchronous to mcko and is guaranteed by design to function correctly. ???? 1 2 3 4 5 mcko mdo mseo evto output data valid
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 32 figure 11. nexus tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 33 3.13.4 external bus interface (ebi) timing table 22 lists the timing information for the external bus interface (ebi). table 22. bus operation timing 1 spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 67 mhz 72 mhz min max min max min max min max 1 clkout period t c 25.0 ? 17.9 ? 15.2 ? 13.3 ? ns signals are measured at 50% v dde . 2 clkout duty cycle t cdc 45% 55% 45% 55% 45% 55% 45% 55% t c 3 clkout rise time t crt ?? 4 ?? 4 ?? 4 ?? 4 ns 4 clkout fall time t cft ?? 4 ?? 4 ?? 4 ?? 4 ns 5 clkout positive edge to output signal invalid or hi-z (hold time) external bus interface cs [0:3] addr[8:31] data[0:31] bdip bg 5 br 7 bb oe rd_wr ta tea ts tsiz[0:1] we /be [0:3] t coh 1.0 6 1.5 ? 1.0 6 1.5 ? 1.0 6 1.5 ? 1.0 6 1.5 ?ns ebts = 0 ebts = 1 hold time selectable via siu_eccr [ebts] bit. clkout positive edge to output signal invalid or hi-z (hold time) calibration bus interface cal_cs [0:3] cal_addr[9:30] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we /be [0:1] t ccoh 1.0 6 1.5 ? 1.0 6 1.5 ? 1.0 6 1.5 ? 1.0 6 1.5 ?ns ebts = 0 ebts = 1 hold time selectable via siu_eccr [ebts] bit.
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 34 6 clkout positive edge to output signal valid (output delay) external bus interface cs [0:3] addr[8:31] data[0:31] bdip bg 5 br 7 bb oe rd_wr ta tea ts tsiz[0:1] we /be [0:3] t cov ? 10.0 6 ? 11.0 ? 7.5 6 8.5 ? 6.0 6 7.0 ? 5.0 6 6.0 ns ebts = 0 ebts = 1 output valid time selectable via siu_eccr [ebts] bit. 6a clkout positive edge to output signal valid (output delay) calibration bus interface cal_cs [0:3] cal_addr[9:30] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we /be [0:1] t ccov ? 11.0 6 ? 12.0 ? 8.5 6 9.5 ? 7.0 6 8.0 ? 6.0 6 7.0 ns ebts = 0 ebts = 1 output valid time selectable via siu_eccr [ebts] bit. 7 input signal valid to clkout positive edge (setup time) external bus interface addr[8:31] data[0:31] bg 7 br 5 bb rd_wr ta tea ts tsiz[0:1] t cis 10.0 ? 7.0 ? 5.0 ? 4.0 ? ns table 22. bus operation timing 1 spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 67 mhz 72 mhz min max min max min max min max
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 35 7a input signal valid to clkout positive edge (setup time) calibration bus interface cal_addr[9:30] cal_data[0:15] cal_rd_wr cal_ts t ccis 11.0 ? 8.0 ? 6.0 ? 4.0 ? ns 8 clkout positive edge to input signal invalid (hold time) external bus interface addr[8:31] data[0:31] bg 7 br 5 bb rd_wr ta tea ts tsiz[0:1] t cih 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns clkout positive edge to input signal invalid (hold time) calibration bus interface cal_addr[9:30] cal_data[0:15] cal_rd_wr cal_ts t ccih 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns 1 ebi timing specified at v dde = 1.6?3.6 v (unless stated otherwise), t a = t l to t h , and cl = 30 pf with dsc = 0b10. 2 speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm): 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; 135 mhz parts allow for 132 mhz system clock + 2% fm; and 147 mhz parts allo w for 144 mhz system clock + 2% fm. 3 the external bus is limited to half the speed of the internal bus. 4 refer to fast pad timing in table 17 and ta b l e 1 8 (different values for 1.8 v and 3.3 v). 5 internal arbitration. 6 ebts = 0 timings are tested and valid at v dde = 2.25?3.6 v only; ebts = 1 timings are tested and valid at v dde = 1.6?3.6 v. 7 external arbitration. table 22. bus operation timing 1 spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 67 mhz 72 mhz min max min max min max min max
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 36 figure 12. clkout timing figure 13. synchronous output timing 1 2 2 3 4 clkout v dde ?? 2 vol_f voh_f 6 5 5 clkout bus 5 output signal output v dde ?? 2 v dde ?? 2 v dde ?? 2 v dde ?? 2 6 5 output signal v dde ?? 2 6
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 37 figure 14. synchronous input timing 3.13.5 external interrupt timing (irq signals) table 23. external interrupt timing 1 1 irq timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 irq pulse-width low t ipwl 3?t cyc 2 irq pulse-width high t ipwh 3?t cyc 3 irq edge-to-edge time 2 2 applies when irq signals are configured for ri sing-edge or falling-edge events, but not both. t icyc 6?t cyc 7 8 clkout input bus 7 8 input signal v dde ?? 2 v dde ?? 2 v dde ?? 2
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 38 figure 15. external interrupt timing 3.13.6 etpu timing figure 16. etpu timing table 24. etpu timing 1 1 etpu timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 etpu output channel pulse width t ocpw 2 2 2 this specification does not in clude the rise and fall times. when calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc irq 1 2 3 1 2 etpu output etpu input and tcrclk
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 39 3.13.7 emios timing figure 17. emios timing 3.13.8 dspi timing table 25. emios timing 1 1 emios timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 emios input pulse width t mipw 4?t cyc 2 emios output pulse width t mopw 1 2 2 this specification does not include the ri se and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fi eld (src) in the pad conf iguration register (pcr). ?t cyc table 26. mpc5566 dspi timing 1, 2 spec characteristic symbol 80 mhz 112 mhz 132 mhz 144 mhz unit min max min max min max min max 1 sck cycle time 3, 4 t sck 24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms 13.6 ns 1.6 ms ? 2 pcs to sck delay 5 t csc 23 ? 15 ? 13 ? 12 ? ns 3 after sck delay 6 t asc 22 ? 14 ? 12 ? 11 ? ns 4 sck duty cycle t sdc (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns ns 5 slave access time (ss active to sout driven) t a ? 25 ? 25 ? 25 ? 25 ns 6 slave sout disable time (ss inactive to sout hi-z, or invalid) t dis ? 25 ? 25 ? 25 ? 25 ns 7pcs x to pcss time t pcsc 4?4?4?4?ns 1 2 emios output emios input
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 40 8pcss to pcs x time t pasc 5?5?5?5?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) t sui 20 2 ?4 20 ? ? ? ? 20 2 3 20 ? ? ? ? 20 2 6 20 ? ? ? ? 20 2 7 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) t hi ?4 7 21 ?4 ? ? ? ? ?4 7 14 ?4 ? ? ? ? ?4 7 12 ?4 ? ? ? ? ?4 7 11 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 18 5 ? ? ? ? 5 25 14 5 ? ? ? ? 5 25 13 5 ? ? ? ? 5 25 12 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 5.5 8 ?5 ? ? ? ? ?5 5.5 4 ?5 ? ? ? ? ?5 5.5 3 ?5 ? ? ? ? ?5 5.5 1 ?5 ? ? ? ? ns ns ns ns 1 all dspi timing specifications use the fastest slew rate (src = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate. dspi timing is specified at v ddeh = 3.0?5.25 v, t a = t l to t h , and cl = 50 pf with src = 0b11. 2 speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm; and 14 7 mhz parts allow for 144 mhz system clock + 2% fm. 3 the minimum sck cycle time restricts the baud ra te selection for the gi ven system clock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. 5 the maximum value is programmable in d spi_ctarx[pssck] and dspi_ctarx[cssck]. 6 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 7 this number is calculated using the smpl_pt field in dspi_mcr set to 0b10. table 26. mpc5566 dspi timing 1, 2 (continued) spec characteristic symbol 80 mhz 112 mhz 132 mhz 144 mhz unit min max min max min max min max
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 41 figure 18. dspi classic spi timing?master, cpha = 0 figure 19. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 42 figure 20. dspi classic spi timing?slave, cpha = 0 figure 21. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 43 figure 22. dspi modified transfer format timing?master, cpha = 0 figure 23. dspi modified transfer format timing?master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 44 figure 24. dspi modified transf er format timing?slave, cpha = 0 figure 25. dspi modified transf er format timing?slave, cpha = 1 figure 26. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 45 3.13.9 eqadc ssi timing figure 27. eqadc ssi timing table 27. eqadc ssi timing characteristics spec rating symbol minimum typical maximum unit 2 fck period (t fck = 1 ? f fck ) 1, 2 1 ss timing specified at v ddeh = 3.0?5.25 v, t a = t l to t h , and cl = 25 pf with src = 0b11. maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 fck duty cycle is not 50% when it is generated throu gh the division of the syst em clock by an odd number. t fck 2? 17t sys_clk 3 clock (fck) high time t fckht t sys_clk ? 6.5 ? 9 ? (t sys_clk ? 6.5) ns 4 clock (fck) low time t fcklt t sys_clk ? 6.5 ? 8 ? (t sys_clk ? 6.5) ns 5 sds lead / lag time t sds_ll ?7.5 ? +7.5 ns 6 sdo lead / lag time t sdo_ll ?7.5 ? +7.5 ns 7 eqadc data setup time (inputs) t eq_su 22 ? ? ns 8 eqadc data hold time (inputs) t eq_ho 1? ? ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 fck sds sdo external device data sample at sdi eqadc data sample at fck falling-edge fck rising-edge
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 46 3.14 fast ethernet ac timing specifications media independent interface (mii) fast ethernet controller (fec) signals use transistor-to-transistor logic (ttl) signal levels compatible with devices operating at 3.3 v. the ti ming specifications for the mii fec signals are independent of the system clock frequency (par t speed designation). 3.14.1 mii fec receive signal timing fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk the receive functions corr ectly up to an fec_rx_clk maximum fr equency of 25 mhz plus one percent. there is no minimum frequency require ment. the processor clock frequenc y must exceed four times the fec_rx_clk frequency. table 28 lists mii fec receive channel timings. figure 28 shows mii fec receive signal timings listed in table 28 . figure 28. mii fec receive signal timing diagram table 28. mii fec re ceive signal timing spec characteristic min. max unit 1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns 2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns 3 fec_rx_clk pulse-width high 35% 65% fec_rx_clk period 4 fec_rx_clk pulse-width low 35% 65% fec_rx_clk period 1 2 fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er 3 4
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 47 3.14.2 mii fec transmit signal timing fec_txd[3:0], fec_tx_en, fec_tx_er, fec_tx_clk the transmitter functions correctly up to the fe c_tx_clk maximum frequency of 25 mhz plus one percent. there is no minimum fre quency requirement. in addition, the processor clock frequency must exceed twice the fec_tx_clk frequency. the transmit outputs (fec_txd[3: 0], fec_tx_en, fec_tx_er) can be programmed to transition from either the rising- or falling-e dge of tx_clk, and the timing is the same in either case. these options allow the use of non-compliant mii phys. refer to the fast ethernet controller (fec) chapter of the device reference manual for details of this option and how to enable it. table 29 lists mii fec transmit channel timings. figure 29 shows mii fec transmit signal timings listed in table 29 . figure 29. mii fec transmit signal timing diagram table 29. mii fec transmit signal timing spec characteristic min. max unit 5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns 6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 25 ns 7 fec_tx_clk pulse-width high 35% 65% fec_tx_clk period 8 fec_tx_clk pulse-width low 35% 65% fec_tx_clk period 6 fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er 5 7 8
mpc5566 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 48 3.14.3 mii fec asynchronous inputs signal timing fec_crs and fec_col table 30 lists mii fec asynchronous input signal timing. figure 30 shows mii fec asynchronous input timing listed in table 30 . figure 30. mii fec asynchron ous inputs timing diagram 3.14.4 mii fec serial management channel timing fec_mdio and fec_mdc table 31 lists mii fec serial manageme nt channel timing. the fec functi ons correctly with a maximum fec_mdc frequency of 2.5 mhz. figure 31 shows mii fec serial manageme nt channel timing listed in table 31 . table 30. mii fec asynchronous inputs signal timing spec characteristic min. max unit 9 fec_crs, fec_col minimum pulse width 1.5 ? fec_tx_clk period table 31. mii fec serial management channel timing spec characteristic min. max unit 10 fec_mdc falling-edge to fec_mdio output invalid (minimum propagation delay) 0? ns 11 fec_mdc falling-edge to fec_mdio output valid (maximum propagation delay) ?25 ns 12 fec_mdio (input) to fec_mdc rising-edge setup 10 ? ns 13 fec_mdio (input) to fec_mdc rising-edge hold 0 ? ns 14 fec_mdc pulse-width high 40% 60% fec_mdc period 15 fec_mdc pulse-width low 40% 60% fec_mdc period fec_crs, fec_col 9
electrical characteristics mpc5566 microcontroller data sheet, rev. 3 freescale 49 figure 31. mii fec serial management channel timing diagram fec_mdc (output) fec_mdio (output) 12 13 fec_mdio (input) 10 14 15 11
mpc5566 microcontroller data sheet, rev. 3 mechanicals freescale semiconductor 50 4 mechanicals 4.1 mpc5566 416 pbga pinout figure 32 , figure 33 , and figure 34 show the pinout for the mpc5566 41 6 pbga package. the alternate fast ethernet controller (fec) signals are mult iplexed with the data calibration bus signals. note the mpc5500 devices are pin compatible for software portability and use the primary function names to label the pins in th e bga diagram. although some devices do not support all the pr imary functions shown in the bga diagram, the muxed and gpio signals on those pins remain available. see the signals chapter in the device reference manual for the signal muxing. figure 32. mpc5566 416 package vss 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 vssa0 an15 mdo11 mdo8 vdd vdd33 vss a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 an12 mdo5 mdo2 vss vdde7 tck tdi d vdd vdde7 tms tdo test e mseo0 jcomp evti evto f mseo1 mcko g rdy h j vss vss vss vss vdde7 vdde7 vdde7 vdde7 k vss vss vss vss vss vss vss vdde7 l vss vdde2 vdde2 vss vss vss vss vdde7 sinb m bdip vss tea vdde2 vdde2 vss vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss vss vss vss vss pcsa3 pcsb4 sckb pcsb2 p we3 vss we2 we1 we0 vdde2 vdde2 vss vss vss vss vss pcsb5 souta sina scka r vdde2 vdde2 tsiz0 rd_wr vdde2 vdde2 vss vdde2 vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp t vdde2 tsiz1 ta vdd33 vss vdde2 vdde2 vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash u ts cntxc rxda rstout v rxdb cnrxc txdb reset w vdde2 y extal aa vdde2 vdd xtal ab vdde2 vss vdd vdde2 vdde5 nc vss vdd vrc33 ac vss vdd vdd33 cntxa vdde5 nc vss vdd vdd33 ad br vss vdd oe bg cnrxa vdde5 clkout vss vdd ae vss vdd vdde2 vdde2 bb cntxb cnrxb vdde5 vss af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an10 an21 an0 an1 etrig 1 etpub 18 etpub 20 etpub 24 etpub 27 gpio 205 etrig 0 etpub 21 etpub 25 etpub 28 etpub 31 etpub 19 etpub 22 etpub 26 etpub 30 etpua 30 etpua 31 vddeh 9 etpub 16 etpub 17 etpub 23 etpub 29 vddeh 8 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a vddeh 6 gpio 204 etpub 15 gpio 203 etpub 14 etpub 13 etpub 11 etpub 9 etpub 12 etpub 7 etpub 5 etpub 8 etpub 10 etpub 3 etpub 2 etpub 4 etpub 6 etpub 0 etpub 1 tcrclk b addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk note: no connect. ac22 & ad23 reserved nc ref bypc
mechanicals mpc5566 microcontroller data sheet, rev. 3 freescale 51 figure 33. mpc5566 416 package left side (view 1 of 2) vss 12345678910111213 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 d vdd e f g h j vss vss vss vss k vss vss vss vss l vss vdde2 vdde2 vss m bdip vss tea vdde2 vdde2 vss n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss p we3 vss we2 we1 we0 vdde2 vdde2 vss r vdde2 vdde2 tsiz0 rd_wr vdde2 vdde2 vss vdde2 t vdde2 tsiz1 ta vdd33 vss vdde2 vdde2 u ts v w vdde2 y aa vdde2 ab vdde2 vss vdd vdde2 ac vss vdd vdd33 ad br vss vdd oe ae vss vdd vdde2 vdde2 af 12345678910111213 an10 an21 an0 an1 etpua 30 etpua 31 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 ref bypc
mpc5566 microcontroller data sheet, rev. 3 mechanicals freescale semiconductor 52 figure 34. mpc5566 416 package right side (view 2 of 2) figure 35. mpc5567 416 package 14 15 16 17 18 19 20 21 22 23 24 25 26 vssa0 an15 mdo11 mdo8 vdd vdd33 vss vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd an12 mdo5 mdo2 vss vdde7 tck tdi vdde7 tms tdo test mseo0 jcomp evti evto mseo1 mcko rdy vdde7 vdde7 vdde7 vdde7 vss vss vss vdde7 vss vss vss vdde7 sinb vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 vss vss vss vss pcsa3 pcsb4 sckb pcsb2 vss vss vss vss pcsb5 souta sina scka vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash cntxc rxda rstout rxdb cnrxc txdb reset extal vdd xtal vdde5 nc vss vdd vrc33 cntxa vdde5 nc vss vdd vdd33 bg cnrxa vdde5 clkout vss vdd bb cntxb cnrxb vdde5 vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 14 15 16 17 18 19 20 21 22 23 24 25 26 etrig 1 etpub 18 etpub 20 etpub 24 etpub 27 gpio 205 etrig 0 etpub 21 etpub 25 etpub 28 etpub 31 etpub 19 etpub 22 etpub 26 etpub 30 vddeh 9 etpub 16 etpub 17 etpub 23 etpub 29 vddeh 8 vddeh 6 gpio 204 etpub 15 gpio 203 etpub 14 etpub 13 etpub 11 etpub 9 etpub 12 etpub 7 etpub 5 etpub 8 etpub 10 etpub 3 etpub 2 etpub 4 etpub 6 etpub 0 etpub 1 tcrclk b data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk note: no connect. ac22 & ad23 reserved nc
mechanicals mpc5566 microcontroller data sheet, rev. 3 freescale 53 4.2 mpc5566 416-pin package dimensions the package drawings of the mpc5566 416 pin tepbga package are shown in figure 36 . figure 36. mpc5566 416 tepbga package
mpc5566 microcontroller data sheet, rev. 3 mechanicals freescale semiconductor 54 figure 36. mpc5566 416 tepbga package (continued)
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 55 5 revision history for the mpc5566 data sheet the history of revisions made to th is data sheet are listed and described in this section. the information that has changed from a previous re vision of this docum ent to the current revision is listed for each revision and are grouped in the following categories: ? global and text changes ? table and figure changes within each category, the information that has changed is listed in sequential order. 5.1 information changed betw een revisions 2.0 and 3.0 the following table lists the information that cha nged in the tables between rev. 2.0 and 3.0. click the links to see the change. 5.2 information changed betw een revisions 1.0 and 2.0 the following table lists the information that cha nged in the tables between rev. 1.0 and 2.0. click the links to see the change. table 32. changes between rev. 2.0 and 3.0 location description of changes section 3.7, ?power-up/down sequencing ? added the following paragraph in section 3.7, ?power-up/down sequencing ? ?during initial power ramp-up, when vstby is 0. 6v or above. a typical current of 1-3ma and maximum of 4ma may be seen until vdd is applie d. this current will not reoccur until vstby is lowered below vstby min. specification?. moved figure 2 (fistby worst-case specifications) to section 3.7, ?power-up/down sequencing ?. section 3.8, ?dc electrical specifications in table 9 (dc electrical specifications (t a = t l to t h )) for spec 27d the characteristic ?refer to figure 3 for an interpolation of this data? changed to ?ram standby current?. changed the footnote attached to idd_stby to ?the current specification relates to average standby operation after sram has been loaded with data. for power up current see section 3.7, ?power-up/down sequencing ?, figure 2 (fistby worst-case specifications) . removed the footnote ?figure 3 shows an illustra tion of the idd_stby values interpolated for these temperature values?.
mpc5566 microcontroller data sheet, rev. 3 revision history for the mpc5566 data sheet freescale semiconductor 56 table 33. changes between rev. 1.0 and 2.0 location description of changes ta b l e 3 , mpc5566 thermal characteristics: changed for production purposes, footnote 1 from: junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient te mperature, air flow, power dissipation of other components on the board , and board thermal resistance. to: junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other board components , and board thermal resistance. ta b l e 6 , vcr/por electrical specifications: added footnote 1 to specs 1, 2, and 3 that reads: on power up, assert reset before v por15 , v por33 , and v por5 negate (internal por). reset must remain asserted un til the power supplies are wit hin the operat ing conditions as specified in table 9 dc electrical specifications . on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. ta b l e 9 , dc electrical specifications: ? added footnote that reads: v dde2 and v dde3 are limited to 2.25?3.6 v only if ebts = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if ebts =1. ? removed footnote to specs 27a, b, and c on the max va lues that read: ?preliminary. specification pending final characterization.? ? removed footnote to specs 27a, b, and c on the max values that read: ?specification pending final characterization.? table 16 , flash biu settings vs. frequency of operation: ? removed footnote 9 in columns apc and rwsc for 14 7 mhz row that read: preliminary setting. final setting pending characterization. table 22 , bus operation timing: ? external bus frequency in the table heading: added footnote that reads: speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, 135 mhz parts allow for 132 mhz system clock + 2% fm; and 147 mhz parts allow for 144 mhz system clock + 2% fm. ? spec 1: changed the values in min. columns: 40 mhz from 25 to 24.4; 56 mhz from 17.9 to 17.5 ? specs 7 and 8: removed from external bus interface: bdip , oe , tsiz[0:1], and we /be [0:3]. ta b l e 2 6 , dspi timing: ? table title: added footnote that reads: speed is the nominal maximu m frequency. max speed is the maximum speed allowed incl uding frequency modulation (fm). 82 mhz part s allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, 135 mhz parts allow for 132 mhz system clock + 2% fm; and 147 mhz parts allow for 144 mhz system clock + 2% fm. ? removed footnote that reads: ?specification pending final characterization.? ? spec 2, pcs to sck delay , 144 mhz, min. 12 ? spec 3, after sck delay , 144 mhz, min. 11 ? spec 9, master (mtfe = 1, cpha = 0) , 144 mhz, min. 7 ? spec 10, master (mtfe = 1, cpha = 0) , 144 mhz, min. 11 ? spec 11, master (mtfe = 1, cpha = 0) , 144 mhz, max. 12 ? spec 12, master (mtfe = 1, cpha = 0) , 144 mhz, min. 1
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 57 5.3 information changed betw een revisions 0.0 and 1.0 the following table lists the global changes made throughout the document, as well as the changes to sections of text not cont ained in a figure or table. table 34. global and text changes between rev. 0.0 and 1.0 location description of changes global changes ? third paragraph and throughout the document, replaced: ? kilobytes with kb. ? megabytes with mb. ? put overbars on the following signals: bb , bg , br , bdip , oe , ta , tea , ts , ? changed we [0:3]/be [0:3] to we /be [0:3]. ? added a 144 mhz system frequency option for the mpc5566 microcontroller. section 1, ?overview ?: ? first paragraph, text changed from ? based on the powerpc book e architecture? to ?built on the power architecture embedded technology.? ? second paragraph: changed terminology from powerpc book e architecture to power architecture terminology. ? added new fourth paragraph about vle feature. ? paragraph nine: changed ?the mpc5566 has an on-ch ip 20-channel enhanced queued analog-to-digital converter (eqadc)? to ?has an on-chip 40-channel dual enhanced queued? ? added paragraph about the fast et hernet controller directly after th e system integratio n unit paragraph. ? added the sentence directly preceding table 1 : ?unless noted in this data sheet, all specifications apply from t l to t h .? 3.7.1, 3.7.2 and 3.7.3: reordered sections resulting in the following order and section renumbering: ? section 3.7.1, ?input value of pins during por dependent on vdd33 ,? then ? section 3.7.2, ?power-up sequence (vrc33 grounded) ,? then ? section 3.7.3, ?power-down sequence (vrc33 grounded) . section 3.7.1, ?input value of pins during por dependent on vdd33 ,? changed: from: ?to avoid accidentally selecting the bypass clock because pllcfg[0:1] and rstcfg are not treated as ones (1s) when por negates, v dd33 must not lag v ddsyn and the reset pin power (v ddeh6 ) when powering the device by more than the v dd33 lag specification in ta b l e 6 . v dd33 individually can lag either v ddsyn or the reset power pin (v ddeh6 ) by more than the v dd33 lag specification. v dd33 can lag one of the v ddsyn or v ddeh6 supplies, but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification only applies during power up. v dd33 has no lead or lag requirements when powering down.? to : ?when powering the device, v dd33 must not lag v ddsyn and the reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in table 6 . this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are no t powered and therefore canno t read the default state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification only applies during power up. v dd33 has no lead or lag requirements when powering down.?
mpc5566 microcontroller data sheet, rev. 3 revision history for the mpc5566 data sheet freescale semiconductor 58 the following table lists the information that change d in the figures or tabl es between rev. 0.0 and 1.0. section 3.7.1, ?input value of pins during por dependent on vdd33 :? added the following text directly before this section and after ta b l e 8 pin status for medium / slow pads during the power-on sequence : ?the values in ta b l e 7 and ta b l e 8 do not include the effect of the weak pull devices on the output pins during power up. before exiting the internal por stat e, the voltage on the pins goes to high-impedance until por negates. when the internal por negates, the functional state of the signal during reset applies and the weak pull devices (up or down) are enabled as defined in the device reference manual . if v dd is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to v dde and v ddeh . to avoid this condition, minimize the ramp time of the v dd supply to a time period less than the time required to enable the external circuitry connected to the device outputs.? section 3.7.3, ?power-down sequence (vrc33 grounded) ? deleted the underscore in ored_por to become ored por. table 35. table and figure changes between rev. 0.0 and rev. 1.0 location description of changes figure 1 , mpc5500 family part numbers: ? removed the 2 in the tape and reel designator in both the graphic and in the t ape and reel status text. ? changed qualification status by adding ?, general mark et flow? to the m designator, and added an ?s? designator with the description of ?fully sp ec. qualified, automotive flow. ta b l e 1 , orderable part numbers: ? added a 144 mhz system frequency option for: ? mpc5566mvr144, pb-free (lead free), nominal 144, maximum 147 ? mpc5566mzp144, snpb (leaded), nominal 144, maximum 147 ? changed the 132 mhz maximum operating frequency to 135 mhz. ? reordered rows to group devices by lead-free package types in descending frequency order, and leaded package types. ? footnote 1 added that reads: all devices are ppc556 6, rather than mpc5566 or spc5566, until product qualifications are complete. not all config urations are available in the ppc parts. ? footnote 2 added that reads: the lowest ambi ent operating temperature is referenced by t l ; the highest ambient operating temperature is referenced by t h . ? changed footnote 3 from ?132 mhz allows only 128 mhz + 2% fm? to ?135 mhz parts allow for 132 mhz systems clock + 2% fm?; and added ?147 mhz parts allow for 144 mhz systems clock + 2% fm. table 34. global and text changes between rev. 0.0 and 1.0 (continued) location description of changes
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 59 ta b l e 2 , absolute maximum ratings: ? deleted spec 3, ?flash core voltage.? ? spec 12 ?dc input voltage?: deleted from second line?. . .except for etpub15 and sinb (dspi_b_sin)? leaving v ddeh powered i/o pads. deleted third line ?v ddeh powered by i/o pads (etpub15 and sinb), including the min. and max values of -0.3 and 6.5 respectively, and deleted old footnote 7. ? spec 12 ?dc input voltage?: added footnote 8 to second line ?v dde powered i/o pads? that reads: ?internal structures hold the input voltage less than t he maximum voltage on all pads powered by the v dde supplies, if the maximum injection current specification is met (s ma for all pins) and v dde is within the operating voltage specifications. ? spec 14, column 2, changed: ?v ss differential voltage? to ?v ss to v ssa differential voltage.? ? spec 15, column 2, changed: ?v dd differential voltage? to ?v dd to v dda differential voltage.? ? spec 21, added the name of the spec, ? v rc33 to v ddsyn differential voltage,? as well as the name and cross reference to table 9 , dc electrical specification s, to which the spec was moved. ? spec 28 ?maximum solder temperature?: added two subordinate lines: lead free (pbfree) and leaded (snpb) with maxi mum values of 260 c and 245 c respectively. ? footnote 1, added: ?any of? betw een ?beyond? and ?the listed maxima.? ? deleted footnote 2: ?absolute maximum voltages are cu rrently maximum burn-in vo ltages. absolute maximum specifications for device stress have not yet been de termined.?spec 26 ?maximum operating temperature range?: replaced -40 c with t l . ? footnote 6 (now footnote 5) : changed to the following sentence to the end, ?internal structures hold the input voltage greater than -1.0 v if the inje ction current limit of 2 ma is met. keep the negative dc voltage greater than -0.6 v on etpu[15] and on sinb during the internal power-on reset (por) state.? ta b l e 4 , emi testing specifications: ? changed the maximum operating frequency to from 132 to f max . ? footnote 2: deleted ?refer to tabl e 1 for the maximum operating frequency.? table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
mpc5566 microcontroller data sheet, rev. 3 revision history for the mpc5566 data sheet freescale semiconductor 60 ta b l e 5 , esd characteristics: added (electromagnet ic static discharge) in the table title. ta b l e 6 , vcr/por electrical specifications: ? added footnote 1 to specs 1, 2, and 3 that reads: on power up, assert reset before v por15 , v por33 , and v por5 negate (internal por). reset must remain asserted unti l the power supplies are within the operating conditions as specified in table 9 dc electrical specifications . on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. ? subscript all symbol names that appear after the first underscore character. ? specs 7 and 10: added ?at tj ? at the end of the first line in the second column: characteristic. ? removed ?tj ? after ?150 c? in the last line, second column: characteristic. ? spec 10, second column, second line: added cross-reference to footnote 6: ?i vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 =3.1 v, v vrcctl = 2.2 v.? changed ?(@ v dd = 1.35 v, f sys = f max )? to ?(@ f sys = f max ).? ? footnote 10: deleted ?preliminary value. fi nal specification pending characterization.? ? added to spec 2: 3.3 v (v ddsyn ) por negated (ramp down) min 0.0 max 0.30 v 3.3 v (v ddsyn ) por asserted (ramp up) min 0.0 max 0.30 v ? added new footnote 1 to both lines in spec 3: ? v il_s ( table 9 , spec 15) is guaranteed to scale with v ddeh6 down to v por5 . ? spec 5: changed old footnote 1 (now footnote 2): ?user must be able to supply full operating current for the 1.5v supply when the 3.3v supply reaches this range.? to ?sup ply full operating current for the 1.5 v supply when the 3.3 v supply reaches this range.? ? spec 3: added new footnote 3 for both lines: ?it is possible to reach the current limit during ramp up--do not treat this event as a short circuit current.? ? spec 10: ? changed the minimum values of: -40 c = 60; 25 c = 65. ? added old footnote 5 new footnote 6. ? added a new footnote 7, ?refer to ta b l e 1 for the maximum operating frequency.? ? rewrote old footnote 7(new footnote 9) to: represents the worst-case external transistor beta. it is measured on a per part basis and calculated as (i dd ?? i vrcctl ). ? deleted old footnote 8: ?preliminary value. final specification pending characterization.? ta b l e 7 , power sequence pin status for fast pads: ? changed title to pin status for fast pads during the power sequence ? changed preceding paragraph from: although there are no power up /down sequencing requirements to prev ent issues like latch-up, excessive current spikes, etc., the state of the i/o pins during pow er up/down varies depending on power. prior to exiting por, the pads are in a high impedance state (hi-z). to: there are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. therefore, the st ate of the i/o pins during power up/down varies depending on which supplies are powered. ? deleted the ?comment? column. ? added a por column after the v dd column. ? added row 2:? v dde , low, low, asserted, high? and row 5: v dde , v dd33 , v dd , asserted, hi-z. ta b l e 8 , power sequence pin status for medium/slow pads: ? changed title to pin status for medium and slow pads during the power sequence ? updated preceding paragraph. ? deleted the ?comment? column. ? added a por column after the v dd column. ? added row 3:? v ddeh , v dd , asserted, hi-z.? table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 61 ta b l e 9 , dc electrical specifications: ? spelled out meaning of the slash ?/? as ?and? as well as ?i/o? as ?input/output.? sentence still very confusing. deleted ?input/output? from t he specs to improve clarity. ? spec 20, column 2, characteristics ,? slow and medium output high voltage (i oh_s = ?2.0 ma):? created a left-justified second line and moved ?i oh_s = ?2.0 ma? from the 1st line to the second line and deleted the parentheses. created a left-j ustified third line that reads ?i oh_s = ?1.0 ma.? ? spec 20, column 4, min : added a blank line before and after ?0.80 ? v ddeh ? and put ?0.85 ? v ddeh ? on the last line. ? spec 22, column 2, ? slow and medium output low voltage (i ol_s = 2.0 ma) :? created a left-justified second line and moved ?i ol_s = 2.0 ma.? from the 1st line to the second line and deleted the parentheses. created a left-justified third line that reads ?i ol_s = 1.0 ma.? ? spec 22, column 5, max : added a blank line before and after ?0.20 ? v ddeh ? and put ?0.15 ? v ddeh ? on the last line. ? spec 26: changed ?an[12]_ma[1 ]_sdo? to ?an[ 13]_ma[1]_sdo?. ? added footnote 10 to specs 27a, b, and c on the 4-way cache line that reads: four-way cache enabled (l1csr0[corg] = 0b1) or (l1csr0[corg] = 0b0 wi th l1csr0[wam] = 0b1, l1csr0[wid] = 0b1111, l1csr0[wdd] = 0b1111, l1csr0[awid] = 0b1, and l1csr0[awdd] = 0b1). ? added footnote 11 to specs 27a, b, and c on the max numeric values: ?preliminary. specification pending final characterization.? ? added footnote 12 to specs 27a, b, and c on the max tbd values: ?specification pending final characterization.? ? spec 27a: operating current 1.5 v supplies @ 132 mhz : changed 132 mhz to 135 mhz. changed maximum values for 8-way cache: all 8-way cache max values have footnote 18. -- 1.65 typical = 630 -- 1.35 typical = 500 -- 1.65 high = 785 -- 1.35 high = 630 changed 4-way cac he with footnote 10: -- 1.65 high = 685 -- 1.35 high = tbd with footnote 19. ? spec 27b, operating current 1.5 v supplies @ 114 mhz : changed maximum values for 8-way cache. all 8-way cache max values have footnote 18: -- 1.65 typical = 600 -- 1.35 typical = 450 -- 1.65 high = 680 -- 1.35 high = 500 changed 4-way cache values: -- 1.65 high = tbd with footnote 19 -- 1.35 high = tbd with footnote 19 ? spec 27c, operating current 1.5 v supplies @ 82 mhz : changed maximum values for 8-way cache: all 8-way cache max values have footnote 18. -- 1.65 typical = 490, -- 1.35 typical = 360, -- 1.65 high = 520, -- 1.35 high = 390. changed 4-way cache values: -- 1.65 high = tbd with footnote 19 -- 1.35 high = tbd with footnote 19 table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
mpc5566 microcontroller data sheet, rev. 3 revision history for the mpc5566 data sheet freescale semiconductor 62 ta b l e 9 , dc electrical specifications (continued) ? spec 27e, operating current 1.5 v supplies @ 147 mhz : added maximum values for 8-wa y cache: all wit h footnote 11. -- 1.65 typical = 650, -- 1.35 typical = 530, -- 1.65 high = 820, -- 1.35 high = 650. added 4-way cache: all with footnote 11. -- 1.65 high = 720 -- 1.35 high = 585 ? spec 28: changed 132 mhz to f max mhz. ? spec 29: deleted @ 132 mhz. ? corrected footnote 3 to read: if stan dby operation is not required, connect the v stby to ground. ? combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line that reads: eight-way cache en abled (l1csr0[corg] = 0b0). ? deleted footnotes 12 and 13 about preliminary specif ications and specification pending characterization. figure 2 , added figure to show interpolated idd stby values listed in ta b l e 9 . ta b l e 1 2 , fmpll electrical characteristics: ? added (t a = t l ? t h ) to the end of the second line in the table title. ? spec 1, footnote 1 in column 2: ?pll reference frequency range ?: changed to read ?nominal crystal and external reference values are worst-case not more than 1%. the de vice operates correctly if the frequency remains within 5% of the specification limit. this tolerance range allows for a slight frequency drift of the crystals over time. the designer must thoroughly understand the drift margin of the source clock.? ? specs 12 and 13: grouped (2 x cl). ? spec 21, column 2: changed f ref_crystal to f ref in ico frequency equation, and added the same equation but substituted f ref_ext for f ref for the external reference clock, giving: f ico = [ f ref_crystal ? (mfd + 4) ] ?? (prediv + 1) f ico = [ f ref_ext ? (mfd + 4) ] ?? (prediv + 1) ? spec 21, column 4, max: dele ted old footnote 18 that reads: the ico frequency can be higher than the maximum allo wable system frequency. for this case, set the cmpll synthesizer control register reduced frequency divider (fmpll_syncr[rfd]) to divi de-by-two (rfd = 0b001). therefore, for a 40 mhz maximum de vice (system frequency), program t he fmpll to generat e 80 mhz at the ico output and then divide-by-two the rf d to provide the 40 mhz system clock.? ? spec 21: changed column 5 from ?f sys ? mhz? to: ?f max ?. ? spec 22: changed column 4, max value from f max to 20, and added footnote 17 to read, ?maximum value for dual controller (1:1) mode is (f max ?? 2) and the predivider set to 1 (fmpll_syncr[prediv] = 0b001).? ta b l e 1 3 , eqadc conversion specifications: added (t a = t l ? t h ) to the table title. ta b l e 1 4 , flash program and erase specifications: ? added (t a = t l ? t h ) to the table title. ? specs 7, 8, 9, and 10 inserted new values for the h7fa flash pre-program and erase times and used the previous values for typical values. -- 48 kb: from 340 to 345 -- 64 kb: from 400 to 415 ? spec 8, 128kb block pre-program and erase time, max column value from 15,000 to 7,500. ? moved footnote 1 from the table title to dire ctly after the ?typical? in the column 5 header. ? footnote 2: changed from: ?initial factory condition: ?? 100 ? program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency.? to: ?initial factory condition: ?? 100 ? program/erase cycles, 25 o c, using a typical supply voltage measured at a minimum system frequency of 80 mhz.? table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 63 ta b l e 1 5 , flash eeprom module life: ? replaced (full temperature range) with (t a = t l ? t h ) in the table title. ? spec 1b, min. column valu e changed from 10,000 to 1,000. ta b l e 1 6 , flash biu settings vs. frequency of operations: ? ?added footnote 1 to the end of the table title, the foot note reads: ?illegal combinations exist. use entries from the same row in this table.? ? added fourth row ?147 mhz? after the ?135 mhz? row and before the ?default setting after reset?: columns dpfen, ipfen, pflim, and bfen are the same as the 135 mhz column. new values for the following columns: apc = 0b011, rwsc = 0b100, wwsc = 0b01. ? moved footnote 2:? for maximum flash performance, set to 0b11? to the ?dpfen? column header. ? deleted the x-refs in the ?dpfen? column for the rows. ? created a x-ref for footnote 2 and inserted in the ?ipfen? column header. ? deleted the x-refs in the ?ipfen? column for the rows. ? moved footnote 3:? for maximum flash performance, set to 0b110? to the ?pflim? column header. ? deleted the x-refs in the ?pflim? column for the rows. ? moved footnote 4:? for maximum flash performance, set to 0b1? to the ?bfen? column header. ? deleted the x-refs in the ?bfen? column for the rows. ? changed footnotes 1, 5, and 6 to become footnotes 5, 6, and 7. added footnote 8. -- footnote 5 82 mhz parts allow for 80 mhz s ystem clock + 2% frequency modulation (fm). -- footnote 6 102 mhz parts allow for 100 mhz system clock + 2% fm. -- footnote 7 135 mhz parts allow for 132 mhz system clock + 2% fm. -- footnote 8 147 mhz parts allow for 144 mhz system clock + 2% fm. ? footnote 9: added to the end of the 1s t column for the 147 mhz row that reads: preliminary setting. final se tting pending characterization. ta b l e 1 7 , pad ac specifications and ta b l e 1 8 , derated pad ac specifications: ? footnote 1, deleted ?f sys = 132 mhz.? ? footnote 2, changed from ?t ested? to ?(not tested).? ? footnote 3, changed from ?out delay. . .? to ?the output delay. . .?, ? changed from ? add a maximum of one system clock to the output delay to get the output delay with respect to the system clock? to ?to calculate the output delay with respect to the system clock, add a maximum of one system clock to th e output delay.? ? footnote 4: changed ?delay? to ?the output delay.? ? footnote 5: deleted ?before qualification.? ? changed from ?this parameter is supplied for reference and is not guaranteed by design and not tested? to ?this parameter is supplied for reference a nd is guaranteed by design and tested.? ta b l e 1 9 , reset and configuration pin timing: footnote 1, deleted ?f sys = 132 mhz.? ta b l e 2 0 , jtag pin ac electrical characteristics: ? footnote 1, deleted: ?, and cl = 30 pf with dsc = 0b10, src = 0b11? ? footnote 1, changed ?functional? to ?nexus.? ta b l e 2 1 , nexus debug port timing. changed spec 12, tck low to tdo data valid: changed ?vdde = 3.0 to 3.6 volts? maximum value in column 4 from 9 to 10. now reads ?v dde = 3.0?3.6 v? with a max value of 10. table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
mpc5566 microcontroller data sheet, rev. 3 revision history for the mpc5566 data sheet freescale semiconductor 64 ta b l e 2 2 , bus operation timing: ? added a column to the table for 72 mhz minimum and maximum bus frequencies. ? spec 1: 72 mhz min. column = 13.3. ? specs 5 and 6: clkout positive edge to output signals invalid of high : corrected format to show the bus timing values for various frequencies with ebts bit = 0 and ebts bit = 1. ? specs 5, and 6: added the bb signal for arbitration. added the followi ng calibration signals: cal_addr[9:30], cal_cs [0:3], cal_data[ 0:15], cal_oe , cal_rd_wr , cal_ts , cal_we /be [0:1]. ? spec 5: ebi and calibration sections, 72 mh z min column, ebts = 0 is 1.0, ebts = 1 is 1.5. ? spec 6: ebi section, 72 mhz max column, ebts = 0 is 5.0, ebts = 1 is 6.0. ? spec 6a: calibration section, 72 mhz max column, ebts = 0 is 6.0, ebts = 1 is 7.0 ? specs 7 and 8: added the bb signal for arbitration. added the follo wing calibration signa ls: cal_addr[9:30], cal_data[0:15], cal_rd_wr , cal_ts . ta b l e 2 3 , external interrupt timing: ? footnote 1: deleted ?. . f sys = 132 mhz?, ?v dd33 and v ddsyn = 3.0?3.6 v? and ? .and cl = 200 pf with src = 0b11.? ? deleted second figure after table ?external interrupt setup timing.? table 24, etpu timing ? footnote 1: deleted ?. . .f sys = 132 mhz?, ?v dd33 and v ddsyn = 3.0?3.6 v? and ?and cl = 200 pf with src = 0b11.? ? deleted second figure, ? etpu input/output timing ? after this table. ? added footnote 2: ?this specification does not include the rise and fall times. when calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate control fields (src) of the pad configuration registers (pcr).? ta b l e 2 5 , emios timing: ? deleted (mts) from the head ing, table, and footnotes. ? footnote 1: deleted ?. . .f sys = 132 mhz, ?v dd33 and v ddsyn = 3.0?3.6 v? and ?and cl = 200 pf with src = 0b11.? ? added footnote 2: ?this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fields (src) of the pad configuration registers (pcr).? figure 17 , emios timing: added figure. ta b l e 2 6 , dspi timing: ? added 144 mhz column to the table. ? spec1: sck cycle time : changes to values: 80 mhz, min. = 24 .4; 112 mhz, min. = 17.5, max = 2.1; 132 mhz, min. = 14.8, max = 1.8; 144 mhz, min. = 13.6, max = 1.6. ? spec1: sck cycle time : added footnote 4 to the 144 mhz min. and max values that reads: preliminary. specification pending final characterization ? spec 2, pcs to sck delay , 144 mhz, min. tbd ? spec 3, after sck delay , 144 mhz, min. tbd ? spec 9, master (mtfe = 1, cpha = 0) , 144 mhz, min. tbd ? spec 10, master (mtfe = 1, cpha = 0) , 144 mhz, min. tbd ? spec 11, master (mtfe = 1, cpha = 0) , 144 mhz, max tbd ? spec 12, master (mtfe = 1, cpha = 0) , 144 mhz, min. tbd ? added to beginning of footnote 1 ?all dspi timing spec ifications use the fastest slew rate (src = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate.? ? footnote 1: deleted ?v dd = 1.35?1.65 v? and ?v dd33 and v ddsyn = 3.0?3.6 v. table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
revision history for the mpc5566 data sheet mpc5566 microcontroller data sheet, rev. 3 freescale 65 ta b l e 2 7 , eqadc ssi timing characteristics: ? deleted from table title ?(pads at 3.3 v or 5.0 v)? ? deleted 1st line in table ?cload = 25 pf on all outputs. pad drive strength set to maximum.? ? spec 1: fck frequency -- removed. ? combined footnotes 1 and 2, and moved the new footnote to spec 2. moved old footnote 3 that is now footnote 2 to spec 2. ? footnote 1, deleted ?v dd = 1.35?1.65 v? and ?v dd33 and v ddsyn = 3.0?3.6 v.? changed ?cl = 50 pf? to ?cl = 25 pf.? ? footnote 2: added ? cycle? after ?duty? to read: fck duty cycle is not 50% when . . . . figure 35 , mpc5566 416 package: deleted the version number and date. table 35. table and figure changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
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